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  1. /*-
  2. * SPDX-License-Identifier: BSD-3-Clause
  3. *
  4. * Copyright (c) 1991 The Regents of the University of California.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. Neither the name of the University nor the names of its contributors
  16. * may be used to endorse or promote products derived from this software
  17. * without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  20. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  23. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29. * SUCH DAMAGE.
  30. *
  31. * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
  32. * $FreeBSD$
  33. */
  34. #ifndef _MACHINE_SPECIALREG_H_
  35. #define _MACHINE_SPECIALREG_H_
  36. /*
  37. * Bits in 386 special registers:
  38. */
  39. #define CR0_PE 0x00000001 /* Protected mode Enable */
  40. #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
  41. #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
  42. #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
  43. #define CR0_PG 0x80000000 /* PaGing enable */
  44. /*
  45. * Bits in 486 special registers:
  46. */
  47. #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
  48. #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
  49. all modes) */
  50. #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
  51. #define CR0_NW 0x20000000 /* Not Write-through */
  52. #define CR0_CD 0x40000000 /* Cache Disable */
  53. #define CR3_PCID_SAVE 0x8000000000000000
  54. #define CR3_PCID_MASK 0xfff
  55. /*
  56. * Bits in PPro special registers
  57. */
  58. #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
  59. #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
  60. #define CR4_TSD 0x00000004 /* Time stamp disable */
  61. #define CR4_DE 0x00000008 /* Debugging extensions */
  62. #define CR4_PSE 0x00000010 /* Page size extensions */
  63. #define CR4_PAE 0x00000020 /* Physical address extension */
  64. #define CR4_MCE 0x00000040 /* Machine check enable */
  65. #define CR4_PGE 0x00000080 /* Page global enable */
  66. #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
  67. #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
  68. #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
  69. #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
  70. #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
  71. #define CR4_PCIDE 0x00020000 /* Enable Context ID */
  72. #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
  73. #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
  74. #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
  75. #define CR4_PKE 0x00400000 /* Protection Keys Enable */
  76. /*
  77. * Bits in AMD64 special registers. EFER is 64 bits wide.
  78. */
  79. #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
  80. #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
  81. #define EFER_LMA 0x000000400 /* Long mode active (R) */
  82. #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
  83. #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
  84. #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
  85. #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
  86. #define EFER_TCE 0x000008000 /* Translation Cache Extension */
  87. /*
  88. * Intel Extended Features registers
  89. */
  90. #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
  91. #define XFEATURE_ENABLED_X87 0x00000001
  92. #define XFEATURE_ENABLED_SSE 0x00000002
  93. #define XFEATURE_ENABLED_YMM_HI128 0x00000004
  94. #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
  95. #define XFEATURE_ENABLED_BNDREGS 0x00000008
  96. #define XFEATURE_ENABLED_BNDCSR 0x00000010
  97. #define XFEATURE_ENABLED_OPMASK 0x00000020
  98. #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
  99. #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
  100. #define XFEATURE_AVX \
  101. (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
  102. #define XFEATURE_AVX512 \
  103. (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
  104. XFEATURE_ENABLED_HI16_ZMM)
  105. #define XFEATURE_MPX \
  106. (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
  107. /*
  108. * CPUID instruction features register
  109. */
  110. #define CPUID_FPU 0x00000001
  111. #define CPUID_VME 0x00000002
  112. #define CPUID_DE 0x00000004
  113. #define CPUID_PSE 0x00000008
  114. #define CPUID_TSC 0x00000010
  115. #define CPUID_MSR 0x00000020
  116. #define CPUID_PAE 0x00000040
  117. #define CPUID_MCE 0x00000080
  118. #define CPUID_CX8 0x00000100
  119. #define CPUID_APIC 0x00000200
  120. #define CPUID_B10 0x00000400
  121. #define CPUID_SEP 0x00000800
  122. #define CPUID_MTRR 0x00001000
  123. #define CPUID_PGE 0x00002000
  124. #define CPUID_MCA 0x00004000
  125. #define CPUID_CMOV 0x00008000
  126. #define CPUID_PAT 0x00010000
  127. #define CPUID_PSE36 0x00020000
  128. #define CPUID_PSN 0x00040000
  129. #define CPUID_CLFSH 0x00080000
  130. #define CPUID_B20 0x00100000
  131. #define CPUID_DS 0x00200000
  132. #define CPUID_ACPI 0x00400000
  133. #define CPUID_MMX 0x00800000
  134. #define CPUID_FXSR 0x01000000
  135. #define CPUID_SSE 0x02000000
  136. #define CPUID_XMM 0x02000000
  137. #define CPUID_SSE2 0x04000000
  138. #define CPUID_SS 0x08000000
  139. #define CPUID_HTT 0x10000000
  140. #define CPUID_TM 0x20000000
  141. #define CPUID_IA64 0x40000000
  142. #define CPUID_PBE 0x80000000
  143. #define CPUID2_SSE3 0x00000001
  144. #define CPUID2_PCLMULQDQ 0x00000002
  145. #define CPUID2_DTES64 0x00000004
  146. #define CPUID2_MON 0x00000008
  147. #define CPUID2_DS_CPL 0x00000010
  148. #define CPUID2_VMX 0x00000020
  149. #define CPUID2_SMX 0x00000040
  150. #define CPUID2_EST 0x00000080
  151. #define CPUID2_TM2 0x00000100
  152. #define CPUID2_SSSE3 0x00000200
  153. #define CPUID2_CNXTID 0x00000400
  154. #define CPUID2_SDBG 0x00000800
  155. #define CPUID2_FMA 0x00001000
  156. #define CPUID2_CX16 0x00002000
  157. #define CPUID2_XTPR 0x00004000
  158. #define CPUID2_PDCM 0x00008000
  159. #define CPUID2_PCID 0x00020000
  160. #define CPUID2_DCA 0x00040000
  161. #define CPUID2_SSE41 0x00080000
  162. #define CPUID2_SSE42 0x00100000
  163. #define CPUID2_X2APIC 0x00200000
  164. #define CPUID2_MOVBE 0x00400000
  165. #define CPUID2_POPCNT 0x00800000
  166. #define CPUID2_TSCDLT 0x01000000
  167. #define CPUID2_AESNI 0x02000000
  168. #define CPUID2_XSAVE 0x04000000
  169. #define CPUID2_OSXSAVE 0x08000000
  170. #define CPUID2_AVX 0x10000000
  171. #define CPUID2_F16C 0x20000000
  172. #define CPUID2_RDRAND 0x40000000
  173. #define CPUID2_HV 0x80000000
  174. /*
  175. * Important bits in the Thermal and Power Management flags
  176. * CPUID.6 EAX and ECX.
  177. */
  178. #define CPUTPM1_SENSOR 0x00000001
  179. #define CPUTPM1_TURBO 0x00000002
  180. #define CPUTPM1_ARAT 0x00000004
  181. #define CPUTPM1_HWP 0x00000080
  182. #define CPUTPM1_HWP_NOTIFICATION 0x00000100
  183. #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
  184. #define CPUTPM1_HWP_PERF_PREF 0x00000400
  185. #define CPUTPM1_HWP_PKG 0x00000800
  186. #define CPUTPM1_HWP_FLEXIBLE 0x00020000
  187. #define CPUTPM2_EFFREQ 0x00000001
  188. /* Intel Processor Trace CPUID. */
  189. /* Leaf 0 ebx. */
  190. #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
  191. #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
  192. #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
  193. #define CPUPT_MTC (1 << 3) /* MTC Supported */
  194. #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
  195. #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
  196. /* Leaf 0 ecx. */
  197. #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
  198. #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
  199. #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
  200. #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
  201. #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
  202. /* Leaf 1 eax. */
  203. #define CPUPT_NADDR_S 0 /* Number of Address Ranges */
  204. #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
  205. #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
  206. #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
  207. /* Leaf 1 ebx. */
  208. #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
  209. #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
  210. #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
  211. #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
  212. /*
  213. * Important bits in the AMD extended cpuid flags
  214. */
  215. #define AMDID_SYSCALL 0x00000800
  216. #define AMDID_MP 0x00080000
  217. #define AMDID_NX 0x00100000
  218. #define AMDID_EXT_MMX 0x00400000
  219. #define AMDID_FFXSR 0x02000000
  220. #define AMDID_PAGE1GB 0x04000000
  221. #define AMDID_RDTSCP 0x08000000
  222. #define AMDID_LM 0x20000000
  223. #define AMDID_EXT_3DNOW 0x40000000
  224. #define AMDID_3DNOW 0x80000000
  225. #define AMDID2_LAHF 0x00000001
  226. #define AMDID2_CMP 0x00000002
  227. #define AMDID2_SVM 0x00000004
  228. #define AMDID2_EXT_APIC 0x00000008
  229. #define AMDID2_CR8 0x00000010
  230. #define AMDID2_ABM 0x00000020
  231. #define AMDID2_SSE4A 0x00000040
  232. #define AMDID2_MAS 0x00000080
  233. #define AMDID2_PREFETCH 0x00000100
  234. #define AMDID2_OSVW 0x00000200
  235. #define AMDID2_IBS 0x00000400
  236. #define AMDID2_XOP 0x00000800
  237. #define AMDID2_SKINIT 0x00001000
  238. #define AMDID2_WDT 0x00002000
  239. #define AMDID2_LWP 0x00008000
  240. #define AMDID2_FMA4 0x00010000
  241. #define AMDID2_TCE 0x00020000
  242. #define AMDID2_NODE_ID 0x00080000
  243. #define AMDID2_TBM 0x00200000
  244. #define AMDID2_TOPOLOGY 0x00400000
  245. #define AMDID2_PCXC 0x00800000
  246. #define AMDID2_PNXC 0x01000000
  247. #define AMDID2_DBE 0x04000000
  248. #define AMDID2_PTSC 0x08000000
  249. #define AMDID2_PTSCEL2I 0x10000000
  250. #define AMDID2_MWAITX 0x20000000
  251. /*
  252. * CPUID instruction 1 eax info
  253. */
  254. #define CPUID_STEPPING 0x0000000f
  255. #define CPUID_MODEL 0x000000f0
  256. #define CPUID_FAMILY 0x00000f00
  257. #define CPUID_EXT_MODEL 0x000f0000
  258. #define CPUID_EXT_FAMILY 0x0ff00000
  259. #ifdef __i386__
  260. #define CPUID_TO_MODEL(id) \
  261. ((((id) & CPUID_MODEL) >> 4) | \
  262. ((((id) & CPUID_FAMILY) >= 0x600) ? \
  263. (((id) & CPUID_EXT_MODEL) >> 12) : 0))
  264. #define CPUID_TO_FAMILY(id) \
  265. ((((id) & CPUID_FAMILY) >> 8) + \
  266. ((((id) & CPUID_FAMILY) == 0xf00) ? \
  267. (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
  268. #else
  269. #define CPUID_TO_MODEL(id) \
  270. ((((id) & CPUID_MODEL) >> 4) | \
  271. (((id) & CPUID_EXT_MODEL) >> 12))
  272. #define CPUID_TO_FAMILY(id) \
  273. ((((id) & CPUID_FAMILY) >> 8) + \
  274. (((id) & CPUID_EXT_FAMILY) >> 20))
  275. #endif
  276. /*
  277. * CPUID instruction 1 ebx info
  278. */
  279. #define CPUID_BRAND_INDEX 0x000000ff
  280. #define CPUID_CLFUSH_SIZE 0x0000ff00
  281. #define CPUID_HTT_CORES 0x00ff0000
  282. #define CPUID_LOCAL_APIC_ID 0xff000000
  283. /*
  284. * CPUID instruction 5 info
  285. */
  286. #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
  287. #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
  288. #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
  289. #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
  290. /*
  291. * MWAIT cpu power states. Lower 4 bits are sub-states.
  292. */
  293. #define MWAIT_C0 0xf0
  294. #define MWAIT_C1 0x00
  295. #define MWAIT_C2 0x10
  296. #define MWAIT_C3 0x20
  297. #define MWAIT_C4 0x30
  298. /*
  299. * MWAIT extensions.
  300. */
  301. /* Interrupt breaks MWAIT even when masked. */
  302. #define MWAIT_INTRBREAK 0x00000001
  303. /*
  304. * CPUID instruction 6 ecx info
  305. */
  306. #define CPUID_PERF_STAT 0x00000001
  307. #define CPUID_PERF_BIAS 0x00000008
  308. /*
  309. * CPUID instruction 0xb ebx info.
  310. */
  311. #define CPUID_TYPE_INVAL 0
  312. #define CPUID_TYPE_SMT 1
  313. #define CPUID_TYPE_CORE 2
  314. /*
  315. * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
  316. */
  317. #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
  318. #define CPUID_EXTSTATE_XSAVEC 0x00000002
  319. #define CPUID_EXTSTATE_XINUSE 0x00000004
  320. #define CPUID_EXTSTATE_XSAVES 0x00000008
  321. /*
  322. * AMD extended function 8000_0007h ebx info
  323. */
  324. #define AMDRAS_MCA_OF_RECOV 0x00000001
  325. #define AMDRAS_SUCCOR 0x00000002
  326. #define AMDRAS_HW_ASSERT 0x00000004
  327. #define AMDRAS_SCALABLE_MCA 0x00000008
  328. #define AMDRAS_PFEH_SUPPORT 0x00000010
  329. /*
  330. * AMD extended function 8000_0007h edx info
  331. */
  332. #define AMDPM_TS 0x00000001
  333. #define AMDPM_FID 0x00000002
  334. #define AMDPM_VID 0x00000004
  335. #define AMDPM_TTP 0x00000008
  336. #define AMDPM_TM 0x00000010
  337. #define AMDPM_STC 0x00000020
  338. #define AMDPM_100MHZ_STEPS 0x00000040
  339. #define AMDPM_HW_PSTATE 0x00000080
  340. #define AMDPM_TSC_INVARIANT 0x00000100
  341. #define AMDPM_CPB 0x00000200
  342. /*
  343. * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
  344. */
  345. #define AMDFEID_CLZERO 0x00000001
  346. #define AMDFEID_IRPERF 0x00000002
  347. #define AMDFEID_XSAVEERPTR 0x00000004
  348. /*
  349. * AMD extended function 8000_0008h ecx info
  350. */
  351. #define AMDID_CMP_CORES 0x000000ff
  352. #define AMDID_COREID_SIZE 0x0000f000
  353. #define AMDID_COREID_SIZE_SHIFT 12
  354. /*
  355. * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
  356. */
  357. #define CPUID_STDEXT_FSGSBASE 0x00000001
  358. #define CPUID_STDEXT_TSC_ADJUST 0x00000002
  359. #define CPUID_STDEXT_SGX 0x00000004
  360. #define CPUID_STDEXT_BMI1 0x00000008
  361. #define CPUID_STDEXT_HLE 0x00000010
  362. #define CPUID_STDEXT_AVX2 0x00000020
  363. #define CPUID_STDEXT_FDP_EXC 0x00000040
  364. #define CPUID_STDEXT_SMEP 0x00000080
  365. #define CPUID_STDEXT_BMI2 0x00000100
  366. #define CPUID_STDEXT_ERMS 0x00000200
  367. #define CPUID_STDEXT_INVPCID 0x00000400
  368. #define CPUID_STDEXT_RTM 0x00000800
  369. #define CPUID_STDEXT_PQM 0x00001000
  370. #define CPUID_STDEXT_NFPUSG 0x00002000
  371. #define CPUID_STDEXT_MPX 0x00004000
  372. #define CPUID_STDEXT_PQE 0x00008000
  373. #define CPUID_STDEXT_AVX512F 0x00010000
  374. #define CPUID_STDEXT_AVX512DQ 0x00020000
  375. #define CPUID_STDEXT_RDSEED 0x00040000
  376. #define CPUID_STDEXT_ADX 0x00080000
  377. #define CPUID_STDEXT_SMAP 0x00100000
  378. #define CPUID_STDEXT_AVX512IFMA 0x00200000
  379. #define CPUID_STDEXT_PCOMMIT 0x00400000
  380. #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
  381. #define CPUID_STDEXT_CLWB 0x01000000
  382. #define CPUID_STDEXT_PROCTRACE 0x02000000
  383. #define CPUID_STDEXT_AVX512PF 0x04000000
  384. #define CPUID_STDEXT_AVX512ER 0x08000000
  385. #define CPUID_STDEXT_AVX512CD 0x10000000
  386. #define CPUID_STDEXT_SHA 0x20000000
  387. #define CPUID_STDEXT_AVX512BW 0x40000000
  388. #define CPUID_STDEXT_AVX512VL 0x80000000
  389. /*
  390. * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
  391. */
  392. #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
  393. #define CPUID_STDEXT2_AVX512VBMI 0x00000002
  394. #define CPUID_STDEXT2_UMIP 0x00000004
  395. #define CPUID_STDEXT2_PKU 0x00000008
  396. #define CPUID_STDEXT2_OSPKE 0x00000010
  397. #define CPUID_STDEXT2_WAITPKG 0x00000020
  398. #define CPUID_STDEXT2_AVX512VBMI2 0x00000040
  399. #define CPUID_STDEXT2_GFNI 0x00000100
  400. #define CPUID_STDEXT2_VAES 0x00000200
  401. #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400
  402. #define CPUID_STDEXT2_AVX512VNNI 0x00000800
  403. #define CPUID_STDEXT2_AVX512BITALG 0x00001000
  404. #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000
  405. #define CPUID_STDEXT2_RDPID 0x00400000
  406. #define CPUID_STDEXT2_CLDEMOTE 0x02000000
  407. #define CPUID_STDEXT2_MOVDIRI 0x08000000
  408. #define CPUID_STDEXT2_MOVDIRI64B 0x10000000
  409. #define CPUID_STDEXT2_ENQCMD 0x20000000
  410. #define CPUID_STDEXT2_SGXLC 0x40000000
  411. /*
  412. * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
  413. */
  414. #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004
  415. #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
  416. #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
  417. #define CPUID_STDEXT3_MCUOPT 0x00000200
  418. #define CPUID_STDEXT3_MD_CLEAR 0x00000400
  419. #define CPUID_STDEXT3_TSXFA 0x00002000
  420. #define CPUID_STDEXT3_PCONFIG 0x00040000
  421. #define CPUID_STDEXT3_IBPB 0x04000000
  422. #define CPUID_STDEXT3_STIBP 0x08000000
  423. #define CPUID_STDEXT3_L1D_FLUSH 0x10000000
  424. #define CPUID_STDEXT3_ARCH_CAP 0x20000000
  425. #define CPUID_STDEXT3_CORE_CAP 0x40000000
  426. #define CPUID_STDEXT3_SSBD 0x80000000
  427. /* MSR IA32_ARCH_CAP(ABILITIES) bits */
  428. #define IA32_ARCH_CAP_RDCL_NO 0x00000001
  429. #define IA32_ARCH_CAP_IBRS_ALL 0x00000002
  430. #define IA32_ARCH_CAP_RSBA 0x00000004
  431. #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
  432. #define IA32_ARCH_CAP_SSB_NO 0x00000010
  433. #define IA32_ARCH_CAP_MDS_NO 0x00000020
  434. #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
  435. #define IA32_ARCH_CAP_TSX_CTRL 0x00000080
  436. #define IA32_ARCH_CAP_TAA_NO 0x00000100
  437. /* MSR IA32_TSX_CTRL bits */
  438. #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001
  439. #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002
  440. /*
  441. * CPUID manufacturers identifiers
  442. */
  443. #define AMD_VENDOR_ID "AuthenticAMD"
  444. #define CENTAUR_VENDOR_ID "CentaurHauls"
  445. #define CYRIX_VENDOR_ID "CyrixInstead"
  446. #define INTEL_VENDOR_ID "GenuineIntel"
  447. #define NEXGEN_VENDOR_ID "NexGenDriven"
  448. #define NSC_VENDOR_ID "Geode by NSC"
  449. #define RISE_VENDOR_ID "RiseRiseRise"
  450. #define SIS_VENDOR_ID "SiS SiS SiS "
  451. #define TRANSMETA_VENDOR_ID "GenuineTMx86"
  452. #define UMC_VENDOR_ID "UMC UMC UMC "
  453. #define HYGON_VENDOR_ID "HygonGenuine"
  454. /*
  455. * Model-specific registers for the i386 family
  456. */
  457. #define MSR_P5_MC_ADDR 0x000
  458. #define MSR_P5_MC_TYPE 0x001
  459. #define MSR_TSC 0x010
  460. #define MSR_P5_CESR 0x011
  461. #define MSR_P5_CTR0 0x012
  462. #define MSR_P5_CTR1 0x013
  463. #define MSR_IA32_PLATFORM_ID 0x017
  464. #define MSR_APICBASE 0x01b
  465. #define MSR_EBL_CR_POWERON 0x02a
  466. #define MSR_TEST_CTL 0x033
  467. #define MSR_IA32_FEATURE_CONTROL 0x03a
  468. #define MSR_IA32_SPEC_CTRL 0x048
  469. #define MSR_IA32_PRED_CMD 0x049
  470. #define MSR_BIOS_UPDT_TRIG 0x079
  471. #define MSR_BBL_CR_D0 0x088
  472. #define MSR_BBL_CR_D1 0x089
  473. #define MSR_BBL_CR_D2 0x08a
  474. #define MSR_BIOS_SIGN 0x08b
  475. #define MSR_PERFCTR0 0x0c1
  476. #define MSR_PERFCTR1 0x0c2
  477. #define MSR_PLATFORM_INFO 0x0ce
  478. #define MSR_MPERF 0x0e7
  479. #define MSR_APERF 0x0e8
  480. #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
  481. #define MSR_MTRRcap 0x0fe
  482. #define MSR_IA32_ARCH_CAP 0x10a
  483. #define MSR_IA32_FLUSH_CMD 0x10b
  484. #define MSR_TSX_FORCE_ABORT 0x10f
  485. #define MSR_BBL_CR_ADDR 0x116
  486. #define MSR_BBL_CR_DECC 0x118
  487. #define MSR_BBL_CR_CTL 0x119
  488. #define MSR_BBL_CR_TRIG 0x11a
  489. #define MSR_BBL_CR_BUSY 0x11b
  490. #define MSR_BBL_CR_CTL3 0x11e
  491. #define MSR_IA32_TSX_CTRL 0x122
  492. #define MSR_IA32_MCU_OPT_CTRL 0x123
  493. #define MSR_SYSENTER_CS_MSR 0x174
  494. #define MSR_SYSENTER_ESP_MSR 0x175
  495. #define MSR_SYSENTER_EIP_MSR 0x176
  496. #define MSR_MCG_CAP 0x179
  497. #define MSR_MCG_STATUS 0x17a
  498. #define MSR_MCG_CTL 0x17b
  499. #define MSR_EVNTSEL0 0x186
  500. #define MSR_EVNTSEL1 0x187
  501. #define MSR_THERM_CONTROL 0x19a
  502. #define MSR_THERM_INTERRUPT 0x19b
  503. #define MSR_THERM_STATUS 0x19c
  504. #define MSR_IA32_MISC_ENABLE 0x1a0
  505. #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
  506. #define MSR_TURBO_RATIO_LIMIT 0x1ad
  507. #define MSR_TURBO_RATIO_LIMIT1 0x1ae
  508. #define MSR_DEBUGCTLMSR 0x1d9
  509. #define MSR_LASTBRANCHFROMIP 0x1db
  510. #define MSR_LASTBRANCHTOIP 0x1dc
  511. #define MSR_LASTINTFROMIP 0x1dd
  512. #define MSR_LASTINTTOIP 0x1de
  513. #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
  514. #define MSR_MTRRVarBase 0x200
  515. #define MSR_MTRR64kBase 0x250
  516. #define MSR_MTRR16kBase 0x258
  517. #define MSR_MTRR4kBase 0x268
  518. #define MSR_PAT 0x277
  519. #define MSR_MC0_CTL2 0x280
  520. #define MSR_MTRRdefType 0x2ff
  521. #define MSR_MC0_CTL 0x400
  522. #define MSR_MC0_STATUS 0x401
  523. #define MSR_MC0_ADDR 0x402
  524. #define MSR_MC0_MISC 0x403
  525. #define MSR_MC1_CTL 0x404
  526. #define MSR_MC1_STATUS 0x405
  527. #define MSR_MC1_ADDR 0x406
  528. #define MSR_MC1_MISC 0x407
  529. #define MSR_MC2_CTL 0x408
  530. #define MSR_MC2_STATUS 0x409
  531. #define MSR_MC2_ADDR 0x40a
  532. #define MSR_MC2_MISC 0x40b
  533. #define MSR_MC3_CTL 0x40c
  534. #define MSR_MC3_STATUS 0x40d
  535. #define MSR_MC3_ADDR 0x40e
  536. #define MSR_MC3_MISC 0x40f
  537. #define MSR_MC4_CTL 0x410
  538. #define MSR_MC4_STATUS 0x411
  539. #define MSR_MC4_ADDR 0x412
  540. #define MSR_MC4_MISC 0x413
  541. #define MSR_RAPL_POWER_UNIT 0x606
  542. #define MSR_PKG_ENERGY_STATUS 0x611
  543. #define MSR_DRAM_ENERGY_STATUS 0x619
  544. #define MSR_PP0_ENERGY_STATUS 0x639
  545. #define MSR_PP1_ENERGY_STATUS 0x641
  546. #define MSR_PPERF 0x64e
  547. #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
  548. #define MSR_IA32_DEBUG_INTERFACE 0xc80 /* Intel Silicon Debug interface */
  549. #define MSR_IA32_PM_ENABLE 0x770
  550. #define MSR_IA32_HWP_CAPABILITIES 0x771
  551. #define MSR_IA32_HWP_REQUEST_PKG 0x772
  552. #define MSR_IA32_HWP_INTERRUPT 0x773
  553. #define MSR_IA32_HWP_REQUEST 0x774
  554. #define MSR_IA32_HWP_STATUS 0x777
  555. /*
  556. * VMX MSRs
  557. */
  558. #define MSR_VMX_BASIC 0x480
  559. #define MSR_VMX_PINBASED_CTLS 0x481
  560. #define MSR_VMX_PROCBASED_CTLS 0x482
  561. #define MSR_VMX_EXIT_CTLS 0x483
  562. #define MSR_VMX_ENTRY_CTLS 0x484
  563. #define MSR_VMX_CR0_FIXED0 0x486
  564. #define MSR_VMX_CR0_FIXED1 0x487
  565. #define MSR_VMX_CR4_FIXED0 0x488
  566. #define MSR_VMX_CR4_FIXED1 0x489
  567. #define MSR_VMX_PROCBASED_CTLS2 0x48b
  568. #define MSR_VMX_EPT_VPID_CAP 0x48c
  569. #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
  570. #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
  571. #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
  572. #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
  573. /*
  574. * X2APIC MSRs.
  575. * Writes are not serializing.
  576. */
  577. #define MSR_APIC_000 0x800
  578. #define MSR_APIC_ID 0x802
  579. #define MSR_APIC_VERSION 0x803
  580. #define MSR_APIC_TPR 0x808
  581. #define MSR_APIC_EOI 0x80b
  582. #define MSR_APIC_LDR 0x80d
  583. #define MSR_APIC_SVR 0x80f
  584. #define MSR_APIC_ISR0 0x810
  585. #define MSR_APIC_ISR1 0x811
  586. #define MSR_APIC_ISR2 0x812
  587. #define MSR_APIC_ISR3 0x813
  588. #define MSR_APIC_ISR4 0x814
  589. #define MSR_APIC_ISR5 0x815
  590. #define MSR_APIC_ISR6 0x816
  591. #define MSR_APIC_ISR7 0x817
  592. #define MSR_APIC_TMR0 0x818
  593. #define MSR_APIC_IRR0 0x820
  594. #define MSR_APIC_ESR 0x828
  595. #define MSR_APIC_LVT_CMCI 0x82F
  596. #define MSR_APIC_ICR 0x830
  597. #define MSR_APIC_LVT_TIMER 0x832
  598. #define MSR_APIC_LVT_THERMAL 0x833
  599. #define MSR_APIC_LVT_PCINT 0x834
  600. #define MSR_APIC_LVT_LINT0 0x835
  601. #define MSR_APIC_LVT_LINT1 0x836
  602. #define MSR_APIC_LVT_ERROR 0x837
  603. #define MSR_APIC_ICR_TIMER 0x838
  604. #define MSR_APIC_CCR_TIMER 0x839
  605. #define MSR_APIC_DCR_TIMER 0x83e
  606. #define MSR_APIC_SELF_IPI 0x83f
  607. #define MSR_IA32_XSS 0xda0
  608. /*
  609. * Intel Processor Trace (PT) MSRs.
  610. */
  611. #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */
  612. #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */
  613. #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */
  614. #define RTIT_CTL_TRACEEN (1 << 0)
  615. #define RTIT_CTL_CYCEN (1 << 1)
  616. #define RTIT_CTL_OS (1 << 2)
  617. #define RTIT_CTL_USER (1 << 3)
  618. #define RTIT_CTL_PWREVTEN (1 << 4)
  619. #define RTIT_CTL_FUPONPTW (1 << 5)
  620. #define RTIT_CTL_FABRICEN (1 << 6)
  621. #define RTIT_CTL_CR3FILTER (1 << 7)
  622. #define RTIT_CTL_TOPA (1 << 8)
  623. #define RTIT_CTL_MTCEN (1 << 9)
  624. #define RTIT_CTL_TSCEN (1 << 10)
  625. #define RTIT_CTL_DISRETC (1 << 11)
  626. #define RTIT_CTL_PTWEN (1 << 12)
  627. #define RTIT_CTL_BRANCHEN (1 << 13)
  628. #define RTIT_CTL_MTC_FREQ_S 14
  629. #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S)
  630. #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S)
  631. #define RTIT_CTL_CYC_THRESH_S 19
  632. #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S)
  633. #define RTIT_CTL_PSB_FREQ_S 24
  634. #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S)
  635. #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4)
  636. #define RTIT_CTL_ADDR0_CFG_S 32
  637. #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S)
  638. #define RTIT_CTL_ADDR1_CFG_S 36
  639. #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S)
  640. #define RTIT_CTL_ADDR2_CFG_S 40
  641. #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S)
  642. #define RTIT_CTL_ADDR3_CFG_S 44
  643. #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S)
  644. #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */
  645. #define RTIT_STATUS_FILTEREN (1 << 0)
  646. #define RTIT_STATUS_CONTEXTEN (1 << 1)
  647. #define RTIT_STATUS_TRIGGEREN (1 << 2)
  648. #define RTIT_STATUS_ERROR (1 << 4)
  649. #define RTIT_STATUS_STOPPED (1 << 5)
  650. #define RTIT_STATUS_PACKETBYTECNT_S 32
  651. #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
  652. #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */
  653. #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2)
  654. #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2)
  655. #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */
  656. #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */
  657. #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */
  658. #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */
  659. #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */
  660. #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */
  661. #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
  662. #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
  663. /* Intel Processor Trace Table of Physical Addresses (ToPA). */
  664. #define TOPA_SIZE_S 6
  665. #define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
  666. #define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
  667. #define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
  668. #define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
  669. #define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
  670. #define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
  671. #define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
  672. #define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
  673. #define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
  674. #define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
  675. #define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
  676. #define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
  677. #define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
  678. #define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
  679. #define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
  680. #define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
  681. #define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
  682. #define TOPA_STOP (1 << 4)
  683. #define TOPA_INT (1 << 2)
  684. #define TOPA_END (1 << 0)
  685. /*
  686. * Constants related to MSR's.
  687. */
  688. #define APICBASE_RESERVED 0x000002ff
  689. #define APICBASE_BSP 0x00000100
  690. #define APICBASE_X2APIC 0x00000400
  691. #define APICBASE_ENABLED 0x00000800
  692. #define APICBASE_ADDRESS 0xfffff000
  693. /* MSR_IA32_FEATURE_CONTROL related */
  694. #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
  695. #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
  696. #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
  697. /* MSR IA32_MISC_ENABLE */
  698. #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
  699. #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
  700. #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
  701. #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
  702. #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
  703. #define IA32_MISC_EN_MONE 0x0000000000040000ULL
  704. #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
  705. #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
  706. #define IA32_MISC_EN_XDD 0x0000000400000000ULL
  707. /*
  708. * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
  709. * document 336996-001 Speculative Execution Side Channel Mitigations.
  710. */
  711. /* MSR IA32_SPEC_CTRL */
  712. #define IA32_SPEC_CTRL_IBRS 0x00000001
  713. #define IA32_SPEC_CTRL_STIBP 0x00000002
  714. #define IA32_SPEC_CTRL_SSBD 0x00000004
  715. /* MSR IA32_PRED_CMD */
  716. #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
  717. /* MSR IA32_FLUSH_CMD */
  718. #define IA32_FLUSH_CMD_L1D 0x00000001
  719. /* MSR IA32_MCU_OPT_CTRL */
  720. #define IA32_RNGDS_MITG_DIS 0x00000001
  721. /* MSR IA32_HWP_CAPABILITIES */
  722. #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
  723. #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
  724. #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
  725. #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
  726. /* MSR IA32_HWP_REQUEST */
  727. #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63)
  728. #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62)
  729. #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61)
  730. #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60)
  731. #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59)
  732. #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42)
  733. #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32)
  734. #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24)
  735. #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16)
  736. #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
  737. #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
  738. /*
  739. * PAT modes.
  740. */
  741. #define PAT_UNCACHEABLE 0x00
  742. #define PAT_WRITE_COMBINING 0x01
  743. #define PAT_WRITE_THROUGH 0x04
  744. #define PAT_WRITE_PROTECTED 0x05
  745. #define PAT_WRITE_BACK 0x06
  746. #define PAT_UNCACHED 0x07
  747. #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
  748. #define PAT_MASK(i) PAT_VALUE(i, 0xff)
  749. /*
  750. * Silicon Debug Interface modes.
  751. */
  752. #define IA32_DEBUG_INTERFACE_EN 0x0000000000000001 /* enable SDBG */
  753. #define IA32_DEBUG_INTERFACE_LOCK 0x0000000040000000 /* lock bit */
  754. #define IA32_DEBUG_INTERFACE_MASK 0x0000000080000000
  755. /*
  756. * Constants related to MTRRs
  757. */
  758. #define MTRR_UNCACHEABLE 0x00
  759. #define MTRR_WRITE_COMBINING 0x01
  760. #define MTRR_WRITE_THROUGH 0x04
  761. #define MTRR_WRITE_PROTECTED 0x05
  762. #define MTRR_WRITE_BACK 0x06
  763. #define MTRR_N64K 8 /* numbers of fixed-size entries */
  764. #define MTRR_N16K 16
  765. #define MTRR_N4K 64
  766. #define MTRR_CAP_WC 0x0000000000000400
  767. #define MTRR_CAP_FIXED 0x0000000000000100
  768. #define MTRR_CAP_VCNT 0x00000000000000ff
  769. #define MTRR_DEF_ENABLE 0x0000000000000800
  770. #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
  771. #define MTRR_DEF_TYPE 0x00000000000000ff
  772. #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
  773. #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
  774. #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
  775. #define MTRR_PHYSMASK_VALID 0x0000000000000800
  776. /*
  777. * Cyrix configuration registers, accessible as IO ports.
  778. */
  779. #define CCR0 0xc0 /* Configuration control register 0 */
  780. #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
  781. non-cacheable */
  782. #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
  783. #define CCR0_A20M 0x04 /* Enables A20M# input pin */
  784. #define CCR0_KEN 0x08 /* Enables KEN# input pin */
  785. #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
  786. #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
  787. state */
  788. #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
  789. assoc */
  790. #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
  791. #define CCR1 0xc1 /* Configuration control register 1 */
  792. #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
  793. #define CCR1_SMI 0x02 /* Enables SMM pins */
  794. #define CCR1_SMAC 0x04 /* System management memory access */
  795. #define CCR1_MMAC 0x08 /* Main memory access */
  796. #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
  797. #define CCR1_SM3 0x80 /* SMM address space address region 3 */
  798. #define CCR2 0xc2
  799. #define CCR2_WB 0x02 /* Enables WB cache interface pins */
  800. #define CCR2_SADS 0x02 /* Slow ADS */
  801. #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
  802. #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
  803. #define CCR2_WT1 0x10 /* WT region 1 */
  804. #define CCR2_WPR1 0x10 /* Write-protect region 1 */
  805. #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
  806. hold state. */
  807. #define CCR2_BWRT 0x40 /* Enables burst write cycles */
  808. #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
  809. #define CCR3 0xc3
  810. #define CCR3_SMILOCK 0x01 /* SMM register lock */
  811. #define CCR3_NMI 0x02 /* Enables NMI during SMM */
  812. #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
  813. #define CCR3_SMMMODE 0x08 /* SMM Mode */
  814. #define CCR3_MAPEN0 0x10 /* Enables Map0 */
  815. #define CCR3_MAPEN1 0x20 /* Enables Map1 */
  816. #define CCR3_MAPEN2 0x40 /* Enables Map2 */
  817. #define CCR3_MAPEN3 0x80 /* Enables Map3 */
  818. #define CCR4 0xe8
  819. #define CCR4_IOMASK 0x07
  820. #define CCR4_MEM 0x08 /* Enables momory bypassing */
  821. #define CCR4_DTE 0x10 /* Enables directory table entry cache */
  822. #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
  823. #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
  824. #define CCR5 0xe9
  825. #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
  826. #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
  827. #define CCR5_LBR1 0x10 /* Local bus region 1 */
  828. #define CCR5_ARREN 0x20 /* Enables ARR region */
  829. #define CCR6 0xea
  830. #define CCR7 0xeb
  831. /* Performance Control Register (5x86 only). */
  832. #define PCR0 0x20
  833. #define PCR0_RSTK 0x01 /* Enables return stack */
  834. #define PCR0_BTB 0x02 /* Enables branch target buffer */
  835. #define PCR0_LOOP 0x04 /* Enables loop */
  836. #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
  837. serialize pipe. */
  838. #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
  839. #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
  840. #define PCR0_LSSER 0x80 /* Disable reorder */
  841. /* Device Identification Registers */
  842. #define DIR0 0xfe
  843. #define DIR1 0xff
  844. /*
  845. * Machine Check register constants.
  846. */
  847. #define MCG_CAP_COUNT 0x000000ff
  848. #define MCG_CAP_CTL_P 0x00000100
  849. #define MCG_CAP_EXT_P 0x00000200
  850. #define MCG_CAP_CMCI_P 0x00000400
  851. #define MCG_CAP_TES_P 0x00000800
  852. #define MCG_CAP_EXT_CNT 0x00ff0000
  853. #define MCG_CAP_SER_P 0x01000000
  854. #define MCG_STATUS_RIPV 0x00000001
  855. #define MCG_STATUS_EIPV 0x00000002
  856. #define MCG_STATUS_MCIP 0x00000004
  857. #define MCG_CTL_ENABLE 0xffffffffffffffff
  858. #define MCG_CTL_DISABLE 0x0000000000000000
  859. #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
  860. #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
  861. #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
  862. #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
  863. #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
  864. #define MC_STATUS_MCA_ERROR 0x000000000000ffff
  865. #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
  866. #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
  867. #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
  868. #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
  869. #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
  870. #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
  871. #define MC_STATUS_PCC 0x0200000000000000
  872. #define MC_STATUS_ADDRV 0x0400000000000000
  873. #define MC_STATUS_MISCV 0x0800000000000000
  874. #define MC_STATUS_EN 0x1000000000000000
  875. #define MC_STATUS_UC 0x2000000000000000
  876. #define MC_STATUS_OVER 0x4000000000000000
  877. #define MC_STATUS_VAL 0x8000000000000000
  878. #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
  879. #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
  880. #define MC_CTL2_THRESHOLD 0x0000000000007fff
  881. #define MC_CTL2_CMCI_EN 0x0000000040000000
  882. #define MC_AMDNB_BANK 4
  883. #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */
  884. #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */
  885. #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */
  886. #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */
  887. #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
  888. #define MC_MISC_AMD_LVT_SHIFT 52
  889. #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */
  890. #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */
  891. #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
  892. #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
  893. #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */
  894. #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */
  895. #define MC_MISC_AMD_CNT_SHIFT 32
  896. #define MC_MISC_AMD_CNT_MAX 0xfff
  897. #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
  898. #define MC_MISC_AMD_PTR_SHIFT 24
  899. /*
  900. * The following four 3-byte registers control the non-cacheable regions.
  901. * These registers must be written as three separate bytes.
  902. *
  903. * NCRx+0: A31-A24 of starting address
  904. * NCRx+1: A23-A16 of starting address
  905. * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
  906. *
  907. * The non-cacheable region's starting address must be aligned to the
  908. * size indicated by the NCR_SIZE_xx field.
  909. */
  910. #define NCR1 0xc4
  911. #define NCR2 0xc7
  912. #define NCR3 0xca
  913. #define NCR4 0xcd
  914. #define NCR_SIZE_0K 0
  915. #define NCR_SIZE_4K 1
  916. #define NCR_SIZE_8K 2
  917. #define NCR_SIZE_16K 3
  918. #define NCR_SIZE_32K 4
  919. #define NCR_SIZE_64K 5
  920. #define NCR_SIZE_128K 6
  921. #define NCR_SIZE_256K 7
  922. #define NCR_SIZE_512K 8
  923. #define NCR_SIZE_1M 9
  924. #define NCR_SIZE_2M 10
  925. #define NCR_SIZE_4M 11
  926. #define NCR_SIZE_8M 12
  927. #define NCR_SIZE_16M 13
  928. #define NCR_SIZE_32M 14
  929. #define NCR_SIZE_4G 15
  930. /*
  931. * The address region registers are used to specify the location and
  932. * size for the eight address regions.
  933. *
  934. * ARRx + 0: A31-A24 of start address
  935. * ARRx + 1: A23-A16 of start address
  936. * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
  937. */
  938. #define ARR0 0xc4
  939. #define ARR1 0xc7
  940. #define ARR2 0xca
  941. #define ARR3 0xcd
  942. #define ARR4 0xd0
  943. #define ARR5 0xd3
  944. #define ARR6 0xd6
  945. #define ARR7 0xd9
  946. #define ARR_SIZE_0K 0
  947. #define ARR_SIZE_4K 1
  948. #define ARR_SIZE_8K 2
  949. #define ARR_SIZE_16K 3
  950. #define ARR_SIZE_32K 4
  951. #define ARR_SIZE_64K 5
  952. #define ARR_SIZE_128K 6
  953. #define ARR_SIZE_256K 7
  954. #define ARR_SIZE_512K 8
  955. #define ARR_SIZE_1M 9
  956. #define ARR_SIZE_2M 10
  957. #define ARR_SIZE_4M 11
  958. #define ARR_SIZE_8M 12
  959. #define ARR_SIZE_16M 13
  960. #define ARR_SIZE_32M 14
  961. #define ARR_SIZE_4G 15
  962. /*
  963. * The region control registers specify the attributes associated with
  964. * the ARRx addres regions.
  965. */
  966. #define RCR0 0xdc
  967. #define RCR1 0xdd
  968. #define RCR2 0xde
  969. #define RCR3 0xdf
  970. #define RCR4 0xe0
  971. #define RCR5 0xe1
  972. #define RCR6 0xe2
  973. #define RCR7 0xe3
  974. #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
  975. #define RCR_RCE 0x01 /* Enables caching for ARR7. */
  976. #define RCR_WWO 0x02 /* Weak write ordering. */
  977. #define RCR_WL 0x04 /* Weak locking. */
  978. #define RCR_WG 0x08 /* Write gathering. */
  979. #define RCR_WT 0x10 /* Write-through. */
  980. #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
  981. /* AMD Write Allocate Top-Of-Memory and Control Register */
  982. #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
  983. #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
  984. #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
  985. /* AMD64 MSR's */
  986. #define MSR_EFER 0xc0000080 /* extended features */
  987. #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
  988. #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
  989. #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
  990. #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
  991. #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
  992. #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
  993. #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
  994. #define MSR_TSC_AUX 0xc0000103
  995. #define MSR_PERFEVSEL0 0xc0010000
  996. #define MSR_PERFEVSEL1 0xc0010001
  997. #define MSR_PERFEVSEL2 0xc0010002
  998. #define MSR_PERFEVSEL3 0xc0010003
  999. #define MSR_K7_PERFCTR0 0xc0010004
  1000. #define MSR_K7_PERFCTR1 0xc0010005
  1001. #define MSR_K7_PERFCTR2 0xc0010006
  1002. #define MSR_K7_PERFCTR3 0xc0010007
  1003. #define MSR_SYSCFG 0xc0010010
  1004. #define MSR_HWCR 0xc0010015
  1005. #define MSR_IORRBASE0 0xc0010016
  1006. #define MSR_IORRMASK0 0xc0010017
  1007. #define MSR_IORRBASE1 0xc0010018
  1008. #define MSR_IORRMASK1 0xc0010019
  1009. #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
  1010. #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
  1011. #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
  1012. #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
  1013. #define MSR_MC0_CTL_MASK 0xc0010044
  1014. #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
  1015. #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
  1016. #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
  1017. #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
  1018. #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
  1019. #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
  1020. #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
  1021. #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
  1022. #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
  1023. #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
  1024. #define MSR_LS_CFG 0xc0011020
  1025. #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
  1026. /* MSR_VM_CR related */
  1027. #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
  1028. /* VIA ACE crypto featureset: for via_feature_rng */
  1029. #define VIA_HAS_RNG 1 /* cpu has RNG */
  1030. /* VIA ACE crypto featureset: for via_feature_xcrypt */
  1031. #define VIA_HAS_AES 1 /* cpu has AES */
  1032. #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
  1033. #define VIA_HAS_MM 4 /* cpu has RSA instructions */
  1034. #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
  1035. /* Centaur Extended Feature flags */
  1036. #define VIA_CPUID_HAS_RNG 0x000004
  1037. #define VIA_CPUID_DO_RNG 0x000008
  1038. #define VIA_CPUID_HAS_ACE 0x000040
  1039. #define VIA_CPUID_DO_ACE 0x000080
  1040. #define VIA_CPUID_HAS_ACE2 0x000100
  1041. #define VIA_CPUID_DO_ACE2 0x000200
  1042. #define VIA_CPUID_HAS_PHE 0x000400
  1043. #define VIA_CPUID_DO_PHE 0x000800
  1044. #define VIA_CPUID_HAS_PMM 0x001000
  1045. #define VIA_CPUID_DO_PMM 0x002000
  1046. /* VIA ACE xcrypt-* instruction context control options */
  1047. #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
  1048. #define VIA_CRYPT_CWLO_ALG_M 0x00000070
  1049. #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
  1050. #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
  1051. #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
  1052. #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
  1053. #define VIA_CRYPT_CWLO_NORMAL 0x00000000
  1054. #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
  1055. #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
  1056. #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
  1057. #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
  1058. #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
  1059. #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
  1060. #endif /* !_MACHINE_SPECIALREG_H_ */